658 search results - page 96 / 132 » Challenges in Physical Chip Design |
165
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MICRO
2007
IEEE
16 years 11 days ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
160
Voted
ICCSA
2007
Springer
16 years 7 days ago
2007
Springer
Abstract. In this work, we develop novel file system, FRASH, for byteaddressable NVRAM (FRAM[1]) and NAND Flash device. Byte addressable NVRAM and NAND Flash is typified by the DRA...
177
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ISCA
2010
IEEE
15 years 8 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
163
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ISCA
2007
IEEE
16 years 12 days ago
2007
IEEE
The ability to perform long, accurate molecular dynamics (MD) simulations involving proteins and other biological macromolecules could in principle provide answers to some of the ...
173
Voted
DAC
2005
ACM
15 years 8 months ago
2005
ACM
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...