28 search results - page 4 / 6 » Challenges in clockgating for a low power ASIC methodology |
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to...
DAC
1998
ACM
15 years 10 months ago
1998
ACM
The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by domin...
ESAS
2004
Springer
15 years 2 months ago
2004
Springer
The common perception of public key cryptography is that it is complex, slow and power hungry, and as such not at all suitable for use in ultra-low power environments like wireless...
SSS
2010
Springer
14 years 7 months ago
2010
Springer
Design and implementation of distributed algorithms often involve many subtleties due to their complex structure, non-determinism, and low atomicity as well as occurrence of unanti...
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...