28 search results - page 5 / 6 » Challenges in clockgating for a low power ASIC methodology |
ASPLOS
2006
ACM
13 years 10 months ago
2006
ACM
We propose regression modeling as an efficient approach for accurately predicting performance and power for various applications executing on any microprocessor configuration in a...
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
The new standard DRM for digital radio broadcast in AM band requires integrated devices for radio receivers at low cost and very low power consumption. A chipset is currently desi...
DAC
2007
ACM
14 years 7 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
IJNSEC
2008
13 years 6 months ago
2008
Secure communication in wireless ad hoc sensor networks is a major research concern in the networking community. Especially the few available resources in terms of processing powe...
VTS
2005
IEEE
13 years 12 months ago
2005
IEEE
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...