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DATE
2006
IEEE
101views Hardware» more  DATE 2006»
15 years 10 months ago
A parallel configuration model for reducing the run-time reconfiguration overhead
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performa...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
ISCA
2009
IEEE
276views Hardware» more  ISCA 2009»
15 years 11 months ago
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (...
Yuejian Xie, Gabriel H. Loh
CCGRID
2005
IEEE
15 years 10 months ago
Experiences with the KOALA co-allocating scheduler in multiclusters
In multicluster systems, and more generally, in grids, jobs may require co-allocation, i.e., the simultaneous allocation of resources such as processors and input files in multip...
Hashim H. Mohamed, Dick H. J. Epema
ISCAS
2005
IEEE
135views Hardware» more  ISCAS 2005»
15 years 9 months ago
Dual use of power lines for data communications in a system-on-chip environment
—We propose to use power pins to simultaneously carry data signals while delivering its power. A direct superposition of a data signal on a power pin would fail due to an inheren...
Woo Cheol Chung, Dong Sam Ha, Hyung-Jin Lee
ASPDAC
2004
ACM
88views Hardware» more  ASPDAC 2004»
15 years 9 months ago
A high performance bus communication architecture through bus splitting
Abstract— A split shared-bus architecture with multiple simultaneous bus accesses is proposed. Compared to traditional bus architectures, the performance of proposed architecture...
Ruibing Lu, Cheng-Kok Koh