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ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
15 years 10 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 9 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
140
Voted
WINET
2010
113views more  WINET 2010»
15 years 3 months ago
Designing multihop wireless backhaul networks with delay guarantees
— As wireless access technologies improve in data rates, the problem focus is shifting towards providing adequate backhaul from the wireless access points to the Internet. Existi...
Girija J. Narlikar, Gordon T. Wilfong, Lisa Zhang
SIGCOMM
2010
ACM
15 years 5 months ago
EffiCuts: optimizing packet classification for memory and throughput
Packet Classification is a key functionality provided by modern routers. Previous decision-tree algorithms, HiCuts and HyperCuts, cut the multi-dimensional rule space to separate ...
Balajee Vamanan, Gwendolyn Voskuilen, T. N. Vijayk...
VLDB
2004
ACM
125views Database» more  VLDB 2004»
16 years 5 months ago
Automatic integration of Web search interfaces with WISE-Integrator
An increasing number of databases are becoming Web accessible through form-based search interfaces, and many of these sources are database-driven E-commerce sites. It is a daunting...
Hai He, Weiyi Meng, Clement T. Yu, Zonghuan Wu