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» Characterizing chip-multiprocessor variability-tolerance
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91
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DATE
2010
IEEE
163views Hardware» more  DATE 2010»
15 years 7 months ago
A methodology for the characterization of process variation in NoC links
—Associated with the ever growing integration scales is the increase in process variability. In the context of networkon-chip, this variability affects the maximum frequency that...
Carles Hernandez, Federico Silla, José Duat...
86
Voted
ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
15 years 10 months ago
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor
In this work we propose a methodology for the accurate analysis of the power consumption of interprocessor communication in a MPSoC, and the construction of high-level power macro...
Mirko Loghi, Luca Benini, Massimo Poncino
104
Voted
CIDR
2007
173views Algorithms» more  CIDR 2007»
15 years 3 months ago
Database Servers on Chip Multiprocessors: Limitations and Opportunities
Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, hi...
Nikos Hardavellas, Ippokratis Pandis, Ryan Johnson...
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
15 years 10 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
IEEEPACT
2008
IEEE
15 years 8 months ago
The PARSEC benchmark suite: characterization and architectural implications
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Sin...