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SBACPAD
2004
IEEE
97views Hardware» more  SBACPAD 2004»
14 years 10 months ago
IATO: A Flexible EPIC Simulation Environment
High-performance superscalar processors are designed with the help of complex simulation environment. The simulation infrastructure permits to validate the processor instruction s...
Amaury Darsch, André Seznec
CCGRID
2006
IEEE
15 years 3 months ago
Statistical Properties of Task Running Times in a Global-Scale Grid Environment
— Over the years, the use of global grid environments have become widespread. In order to make applications robust against the dynamics of those grid environments it is essential...
Menno Dobber, Robert D. van der Mei, Ger Koole
SIGECOM
2005
ACM
169views ECommerce» more  SIGECOM 2005»
15 years 3 months ago
Online auctions with re-usable goods
This paper concerns the design of mechanisms for online scheduling in which agents bid for access to a re-usable resource such as processor time or wireless network access. Each a...
Mohammad Taghi Hajiaghayi, Robert D. Kleinberg, Mo...
ICC
2009
IEEE
113views Communications» more  ICC 2009»
15 years 4 months ago
Green Support for PC-Based Software Router: Performance Evaluation and Modeling
—We consider a new generation of COTS Software Routers (SRs), able to effectively exploit multi-Core/CPU HW platforms. Our main objective is to evaluate and to model the impact o...
Raffaele Bolla, Roberto Bruschi, Andrea Ranieri
ISCA
2000
IEEE
111views Hardware» more  ISCA 2000»
15 years 1 months ago
Understanding the backward slices of performance degrading instructions
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
Craig B. Zilles, Gurindar S. Sohi