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DATE
2007
IEEE
97views Hardware» more  DATE 2007»
15 years 3 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
SAMOS
2007
Springer
15 years 3 months ago
Evaluating Large System-on-Chip on Multi-FPGA Platform
This paper presents a configurable base architecture tailorable for different applications. It allows simple and rapid way to evaluate and prototype large Multi-Processor System-on...
Ari Kulmala, Erno Salminen, Timo D. Hämä...
RTSS
2007
IEEE
15 years 3 months ago
Response-Time Analysis for Globally Scheduled Symmetric Multiprocessor Platforms
In the last years, a progressive migration from single processor chips to multi-core computing devices has taken place in the general-purpose and embedded system market. The devel...
Marko Bertogna, Michele Cirinei
83
Voted
IEEEPACT
2009
IEEE
14 years 7 months ago
ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs
Abstract--Chip-MultiProcessor (CMP) architectures are becoming more and more popular as an alternative to the traditional processors that only extract instruction-level parallelism...
Carlos Luque, Miquel Moretó, Francisco J. C...
92
Voted
DATE
2010
IEEE
113views Hardware» more  DATE 2010»
15 years 2 months ago
PM-COSYN: PE and memory co-synthesis for MPSoCs
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang