509 search results - page 82 / 102 » Chip Multi-Processor Generator |
114
Voted
ISSS
1999
IEEE
15 years 4 months ago
1999
IEEE
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
99
Voted
ISPD
1997
ACM
15 years 3 months ago
1997
ACM
- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for...
85
Voted
SIGGRAPH
1994
ACM
15 years 3 months ago
1994
ACM
FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. ...
ARC
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. Conventional rigid router-based networks on chip incur certain overheads due to huge occupied logic resources and topology embedding, i.e., the mapping of a logical netwo...
102
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DAC
2010
ACM
15 years 3 months ago
2010
ACM
Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can ...