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135
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LPNMR
2009
Springer
15 years 9 months ago
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
130
Voted
SIGMETRICS
2009
ACM
134views Hardware» more  SIGMETRICS 2009»
15 years 9 months ago
DRAM errors in the wild: a large-scale field study
Errors in dynamic random access memory (DRAM) are a common form of hardware failure in modern compute clusters. Failures are costly both in terms of hardware replacement costs and...
Bianca Schroeder, Eduardo Pinheiro, Wolf-Dietrich ...
128
Voted
CGO
2008
IEEE
15 years 9 months ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...
141
Voted
CGO
2008
IEEE
15 years 9 months ago
Spice: speculative parallel iteration chunk execution
The recent trend in the processor industry of packing multiple processor cores in a chip has increased the importance of automatic techniques for extracting thread level paralleli...
Easwaran Raman, Neil Vachharajani, Ram Rangan, Dav...
119
Voted
ICCAD
2008
IEEE
130views Hardware» more  ICCAD 2008»
15 years 9 months ago
Area-I/O flip-chip routing for chip-package co-design
— The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O’s in VLSI designs; it can achieve smaller package size, shorter wirelength, an...
Jia-Wei Fang, Yao-Wen Chang