Sciweavers

1769 search results - page 135 / 354
» Choice in Dynamic Linking
Sort
View
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
15 years 8 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...
SENSYS
2006
ACM
15 years 11 months ago
ATPC: adaptive transmission power control for wireless sensor networks
Extensive empirical studies presented in this paper confirm that the quality of radio communication between low power sensor devices varies significantly with time and environme...
Shan Lin, Jingbin Zhang, Gang Zhou, Lin Gu, John A...
CISIS
2010
IEEE
15 years 11 months ago
Threaded Dynamic Memory Management in Many-Core Processors
—Current trends in desktop processor design have been toward many-core solutions with increased parallelism. As the number of supported threads grows in these processors, it may ...
Edward C. Herrmann, Philip A. Wilsey
ECOOP
2005
Springer
15 years 10 months ago
Prototypes with Multiple Dispatch: An Expressive and Dynamic Object Model
Two object-oriented programming language paradigms— dynamic, prototype-based languages and multi-method languages— provide orthogonal benefits to software engineers. These two...
Lee Salzman, Jonathan Aldrich
PLDI
2010
ACM
15 years 10 months ago
Supporting speculative parallelization in the presence of dynamic data structures
The availability of multicore processors has led to significant interest in compiler techniques for speculative parallelization of sequential programs. Isolation of speculative s...
Chen Tian, Min Feng, Rajiv Gupta