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DAC
1999
ACM

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Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits

13 years 10 months ago

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This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used...

Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...

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DATE
2004
IEEE

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Hierarchical Modeling and Simulation of Large Analog Circuits

13 years 10 months ago

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This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...

Sheldon X.-D. Tan, Zhenyu Qi, Hang Li

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ASPDAC
2007
ACM

152views Hardware» more ASPDAC 2007»

A Graph Reduction Approach to Symbolic Circuit Analysis

13 years 10 months ago

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A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...

Guoyong Shi, Weiwei Chen, C.-J. Richard Shi

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DATE
2000
IEEE

91views Hardware» more DATE 2000»

A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits

13 years 10 months ago