53 search results - page 2 / 11 » Circuit Synthesis of Clock Distribution Networks Based on No... |
ISQED
2007
IEEE
14 years 18 days ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
ISPD
2006
ACM
14 years 9 days ago
2006
ACM
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
ASPDAC
2010
ACM
13 years 4 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
ISQED
2010
IEEE
14 years 1 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
ICCAD
2005
IEEE
14 years 3 months ago
2005
IEEE
Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variation...