366 search results - page 17 / 74 » Circuit optimization using statistical static timing analysi... |
ICCAD
1999
IEEE
15 years 4 months ago
1999
IEEE
A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay . We describe a new delay optimi...
JPDC
2011
14 years 6 months ago
2011
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource ...
DAC
1994
ACM
15 years 3 months ago
1994
ACM
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
DAC
2005
ACM
16 years 21 days ago
2005
ACM
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...
VLSID
2007
IEEE
16 years 3 days ago
2007
IEEE
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...