366 search results - page 19 / 74 » Circuit optimization using statistical static timing analysi... |
117
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DAC
2004
ACM
16 years 21 days ago
2004
ACM
CT An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation is described. The algorithm derives the entire ...
101
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DAC
2000
ACM
15 years 4 months ago
2000
ACM
Abstract: This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circ...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for ci...
DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
ITC
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...