366 search results - page 22 / 74 » Circuit optimization using statistical static timing analysi... |
ASPDAC
2006
ACM
15 years 5 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
109
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DAC
2006
ACM
16 years 22 days ago
2006
ACM
Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...
55
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ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
PATMOS
2005
Springer
15 years 5 months ago
2005
Springer
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
107
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CODES
2009
IEEE
15 years 6 months ago
2009
IEEE
The FlexRay bus is the prospective automotive standard communication system. For the sake of a high flexibility, the protocol includes a static time-triggered and a dynamic event...