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DAC
2007
ACM
16 years 23 days ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
16 years 11 days ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
INFOCOM
2003
IEEE
15 years 5 months ago
Static and Dynamic Analysis of the Internet's Susceptibility to Faults and Attacks
— We analyze the susceptibility of the Internet to random faults, malicious attacks, and mixtures of faults and attacks. We analyze actual Internet data, as well as simulated dat...
Seung-Taek Park, Alexy Khrabrov, David M. Pennock,...
PE
2007
Springer
137views Optimization» more  PE 2007»
14 years 11 months ago
A prediction method for job runtimes on shared processors: Survey, statistical analysis and new avenues
Grid computing is an emerging technology by which huge numbers of processors over the world create a global source of processing power. Their collaboration makes it possible to pe...
Menno Dobber, Robert D. van der Mei, Ger Koole
ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
15 years 6 months ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...