366 search results - page 31 / 74 » Circuit optimization using statistical static timing analysi... |
CF
2007
ACM
15 years 3 months ago
2007
ACM
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
In today’s embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the u...
TCAD
2008
14 years 11 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
DAS
2010
Springer
15 years 3 months ago
2010
Springer
Most of the Indian scripts do not have any robust commercial OCRs. Many of the laboratory prototypes report reasonable results at recognition/classification stage. However, word ...
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ISPD
2012
ACM
13 years 7 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...