366 search results - page 32 / 74 » Circuit optimization using statistical static timing analysi... |
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
100
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VLSID
2004
IEEE
16 years 5 days ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper presents a systematic and optimal design of hybrid cascode compensation method which is used in fully differential two-stage CMOS operational transconductance amplifier...
130
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DAC
2004
ACM
15 years 3 months ago
2004
ACM
The ability to control the variations in IC fabrication process is rapidly diminishing as feature sizes continue towards the sub-100 nm regime. As a result, there is an increasing...
ICCAD
2004
IEEE
15 years 8 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...