366 search results - page 33 / 74 » Circuit optimization using statistical static timing analysi... |
TCAD
2010
14 years 10 months ago
2010
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
114
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ICCAD
1999
IEEE
15 years 4 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
ICCAD
2004
IEEE
15 years 8 months ago
2004
IEEE
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
GLVLSI
2006
IEEE
15 years 5 months ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
106
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IJPP
2000
14 years 11 months ago
2000
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...