366 search results - page 35 / 74 » Circuit optimization using statistical static timing analysi... |
GLVLSI
2005
IEEE
15 years 5 months ago
2005
IEEE
We perform a detailed study of various crosstalk scenarios in VDSM technologies by using a distributed model of the crosstalk site and make a number of key observations about the ...
106
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DAC
2000
ACM
16 years 23 days ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
109
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TVLSI
2008
14 years 11 months ago
2008
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
RV
2010
Springer
14 years 10 months ago
2010
Springer
Researchers have developed a number of runtime verification tools that generate runtime monitors in the form of AspectJ aspects. In this work, we present Clara, a novel framework ...
120
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CODES
2010
IEEE
14 years 9 months ago
2010
IEEE
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...