366 search results - page 7 / 74 » Circuit optimization using statistical static timing analysi... |
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
DATE
2007
IEEE
15 years 3 months ago
2007
IEEE
— We present a waveform based variational static timing analysis methodology. It is a timing paradigm that lies midway between convention static delay approximations and full dyn...
ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance low-power deep-submicrometer digital integrated circuits. An important c...
73
Voted
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing anal...
88
Voted
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...