366 search results - page 8 / 74 » Circuit optimization using statistical static timing analysi... |
89
Voted
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
100
Voted
ISCAS
2003
IEEE
15 years 2 months ago
2003
IEEE
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical met...
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
70
Voted
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
FPGA
2010
ACM
15 years 6 months ago
2010
ACM
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...