366 search results - page 9 / 74 » Circuit optimization using statistical static timing analysi... |
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
79
Voted
PATMOS
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...
ISQED
2007
IEEE
15 years 3 months ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
Abstract-- In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as self-resetting or delayed-reset domino ci...
87
Voted
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a “device file setting” ...