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SAC
2010
ACM
15 years 5 months ago
MSP algorithm: multi-robot patrolling based on territory allocation using balanced graph partitioning
This article addresses the problem of efficient multi-robot patrolling in a known environment. The proposed approach assigns regions to each mobile agent. Every region is represen...
David Portugal, Rui Rocha
114
Voted
FPGA
2001
ACM
152views FPGA» more  FPGA 2001»
15 years 2 months ago
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
Jörg Ritter, Paul Molitor
86
Voted
PADS
1996
ACM
15 years 2 months ago
Conservative Circuit Simulation on Shared-Memory Multiprocessors
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend th...
Jörg Keller, Thomas Rauber, Bernd Rederlechne...
ICCAD
1999
IEEE
89views Hardware» more  ICCAD 1999»
15 years 2 months ago
A bipartition-codec architecture to reduce power in pipelined circuits
This paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of ...
Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-J...
ISLPED
1995
ACM
122views Hardware» more  ISLPED 1995»
15 years 1 months ago
A multiple clocking scheme for low power RTL design
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...
Christos A. Papachristou, Mark Spining, Mehrdad No...