We study the complexity of securely evaluating arithmetic circuits over finite rings. This question is motivated by natural secure computation tasks. Focusing mainly on the case o...
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new ...
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
We have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for...
— We have entered an era where chip yields are decreasing with scaling. A new concept called intelligible testing has been previously proposed with the goal of reversing this tre...