Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
Disk performance is increasingly limited by its head positioning latencies, i.e., seek time and rotational delay. To reduce the head positioning latencies, we propose a novel tech...
Singleton types are often considered a poor man’s substitute for dependent types. But their generalization in the form of GADTs has found quite a following. The main advantage o...