191 search results - page 10 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
ICCD
2001
IEEE
15 years 6 months ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
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DAC
1997
ACM
15 years 1 months ago
1997
ACM
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
ISLPED
1996
ACM
15 years 1 months ago
1996
ACM
In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power ba...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
ISVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Thermal management is becoming increasingly important in circuit designs with high power density. Circuits that overheat beyond specified operating conditions may suffer timing f...