191 search results - page 15 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
102
click to vote
ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
GLVLSI
2003
IEEE
15 years 2 months ago
2003
IEEE
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
VLSI
2010
Springer
14 years 7 months ago
2010
Springer
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...
101
click to vote
ISPD
2004
ACM
15 years 2 months ago
2004
ACM
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...