191 search results - page 18 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
VLSID
2006
IEEE
15 years 3 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
ARVLSI
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
TCAD
1998
14 years 9 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
HPCA
1998
IEEE
15 years 1 months ago
1998
IEEE
The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making an...
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ICCAD
2010
IEEE
14 years 7 months ago
2010
IEEE
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...