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» Clock Distribution Design in VLSI Circuits. An Overview
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ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
15 years 1 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean
SPAA
2000
ACM
15 years 1 months ago
Compact, multilayer layout for butterfly fat-tree
Modern VLSI processing supports a two-dimensional surface for active devices along with multiple stacked layers of interconnect. With the advent of planarization, the number of la...
André DeHon
GLVLSI
2009
IEEE
172views VLSI» more  GLVLSI 2009»
15 years 1 months ago
Contact merging algorithm for efficient substrate noise analysis in large scale circuits
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
Emre Salman, Renatas Jakushokas, Eby G. Friedman, ...
PARLE
1987
15 years 29 days ago
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a pr...
Peter H. Welch
EUROCAST
2001
Springer
106views Hardware» more  EUROCAST 2001»
15 years 2 months ago
On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata
CAST.FSM denotes a CAST tool which has been developed at the Institute of Systems Science at the University of Linz during the years 1986-1993. The first version of CAST.FSM was i...
Michael Affenzeller, Franz Pichler, Rudolf Mittelm...