191 search results - page 25 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
104
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SENSYS
2009
ACM
15 years 4 months ago
2009
ACM
Clock synchronization is highly desirable in many sensor networking applications. It enables event ordering, coordinated actuation, energy-efficient communication and duty cyclin...
78
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ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for hig...
DATE
1999
IEEE
15 years 1 months ago
1999
IEEE
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
TCAD
2002
14 years 9 months ago
2002
A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS...