191 search results - page 26 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
FCCM
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...
HPCA
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...
GECCO
2009
Springer
15 years 4 months ago
2009
Springer
VLSI research, in its continuous push toward further miniaturisation, is seeking to break through the limitations of current circuit manufacture techniques by moving towards biomi...
ASPDAC
1998
ACM
15 years 1 months ago
1998
ACM
— Simple yet useful analytical formulas for delay, slope and crosstalk noise amplitude for capacitively coupled two-, three- and infinite-line systems are derived assuming bus li...
85
Voted
ICCD
1997
IEEE
15 years 1 months ago
1997
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...