191 search results - page 27 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
76
Voted
ASYNC
2002
IEEE
15 years 2 months ago
2002
IEEE
In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease...
ISPD
2003
ACM
15 years 2 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
83
Voted
GLVLSI
2008
IEEE
15 years 3 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
ICRA
2000
IEEE
15 years 1 months ago
2000
IEEE
Our goal is to develop an autonomous robot that will fit within a two-inch cube and will locomote by walking and jumping. The robot will be based on the kinematics of a cricket. I...
DAC
1998
ACM
15 years 10 months ago
1998
ACM
In this paper we present a statistical method for estimating the maximum power consumption in VLSI circuits. The method is based on the theory of extreme order statistics applied ...