191 search results - page 30 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
VLSID
2005
IEEE
15 years 9 months ago
2005
IEEE
Two Simple structures of low-power Dual-edge triggered Static Pulsed Flip-Flops (DSPFF) are presented in this paper. They are composed of a dualedge pulse generator and a static f...
GLVLSI
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper presents a hybrid adiabatic content addressable memory (CAM). The CAM uses an adiabatic switching technique to reduce the energy consumption in the match line while kee...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Models of simulation program with integrated circuit emphasis (SPICE) are currently playing a central role in the connection between circuit design and chip fabrication communitie...
DAC
2001
ACM
15 years 10 months ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...