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» Clock Distribution Design in VLSI Circuits. An Overview
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ISQED
2007
IEEE
236views Hardware» more  ISQED 2007»
15 years 3 months ago
3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method
Due to the roaring power dissipation and gaining popularity of 3D integration, thermal dissipation has been a critical concern of modern VLSI design. The availability for chip-lev...
Dongkeun Oh, Charlie Chung-Ping Chen, Yu Hen Hu
DAC
2007
ACM
15 years 10 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
GLVLSI
2005
IEEE
110views VLSI» more  GLVLSI 2005»
15 years 3 months ago
QCA channel routing with wire crossing minimization
Quantum-dot Cellular Automata (QCA) is a novel computing mechanism that can represent binary information based on spatial distribution of electron charge configuration in chemica...
Brian Stephen Smith, Sung Kyu Lim
GLVLSI
2006
IEEE
113views VLSI» more  GLVLSI 2006»
15 years 3 months ago
Statistical gate delay calculation with crosstalk alignment consideration
We study gate delay variation caused by crosstalk aggressor alignment, i.e., difference of signal arrival times in coupled neighboring interconnects. This effect is as significan...
Andrew B. Kahng, Bao Liu, Xu Xu
HPCA
2005
IEEE
15 years 3 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...