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» Clock Distribution Design in VLSI Circuits. An Overview
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CDC
2008
IEEE
128views Control Systems» more  CDC 2008»
15 years 3 months ago
Time-robust discrete control over networked Loosely Time-Triggered Architectures
In this paper we consider Loosely Time-Triggered Architectures (LTTA) as a networked infrastructure for deploying discrete control. LTTA are distributed architectures in which 1/ ...
Paul Caspi, Albert Benveniste
CF
2005
ACM
14 years 11 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
93
Voted
ISLPED
2003
ACM
90views Hardware» more  ISLPED 2003»
15 years 2 months ago
Understanding and minimizing ground bounce during mode transition of power gating structures
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel

Publication
279views
16 years 7 months ago
Potential Networking Applications of Global Positioning Systems (GPS)
Global Positioning System (GPS) Technology allows precise determination of location, velocity, direction, and time. The price of GPS receivers is falling rapidly and the applicatio...
G. Dommety and Raj Jain
75
Voted
DAC
2002
ACM
15 years 10 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...