191 search results - page 36 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
ISPD
2007
ACM
14 years 11 months ago
2007
ACM
When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge...
SAC
2006
ACM
15 years 3 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
79
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SBCCI
2005
ACM
15 years 3 months ago
2005
ACM
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
104
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DAC
2009
ACM
15 years 10 months ago
2009
ACM
Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-chip communication bottleneck and improve performance over traditional two-dimensional...
ISCAS
1999
IEEE
15 years 1 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...