191 search results - page 3 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
ISPD
2005
ACM
13 years 11 months ago
2005
ACM
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
ASPDAC
2010
ACM
13 years 4 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
VLSID
2005
IEEE
14 years 6 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
ISVLSI
2008
IEEE
14 years 20 days ago
2008
IEEE
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires ...