191 search results - page 7 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
ARVLSI
1999
IEEE
15 years 1 months ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
ICCD
2001
IEEE
15 years 6 months ago
2001
IEEE
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked...
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
DAC
1997
ACM
15 years 1 months ago
1997
ACM
: Academic clock routing research results has often had limited impact on industry practice, since such practical considerations as hierarchical buffering, rise-time and overshoot ...
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...