191 search results - page 9 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
Under modern VLSI technology, process variations greatly affect circuit performance, especially clock skew which is very timing sensitive. Unwanted skew due to process variation f...
IPPS
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper? provides a description of our Network Time Interface M-Module NTI supporting high-accuracy external clock synchronization by hardware. The NTI is built around our custo...
ACSD
2005
IEEE
15 years 3 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
DAC
1991
ACM
15 years 29 days ago
1991
ACM
REX is a program that extracts parasitic resistance and capacitance values for nodes in VLSI layouts. REX also performs network serial and parallel simplifications. Two types of n...