9 search results - page 2 / 2 » Clock Skew Evaluation Considering Manufacturing Variability ... |
75
Voted
ISPD
2005
ACM
15 years 3 months ago
2005
ACM
In the nanometer VLSI technology, the variation effects like manufacturing variation, power supply noise, temperature etc. become very significant. As one of the most vital nets...
DAC
2009
ACM
15 years 4 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
102
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ICCAD
1999
IEEE
15 years 1 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
71
Voted
WISEC
2010
ACM
15 years 4 months ago
2010
ACM
The problem of localizing in-band wormhole tunnels in MANETs is considered. In an in-band wormhole attack, colluding attackers use a covert tunnel to create the illusion that two ...