Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global cloc...
Michael N. Horak, Steven M. Nowick, Matthew Carlbe...
Based on experience in orchestrating co llaborative learning scenarios with ubiquitous computing technology, two strategies for extending a co -constructive modeling environment w...
Abstract—This paper proposes a novel discrete time secondorder distributed consensus time synchronization (SO-DCTS) algorithm for wireless sensor networks. The consensus properti...
Abstract— A fundamental building block in distributed wireless sensor networks is time synchronization. Given resource constrained nature of sensor networks, traditional time syn...