205 search results - page 10 / 41 » Clock gating architectures for FPGA power reduction |
ISLPED
1995
ACM
15 years 1 months ago
1995
ACM
We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transfor...
FCCM
2009
IEEE
15 years 1 months ago
2009
IEEE
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
FPGA
2004
ACM
15 years 2 months ago
2004
ACM
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
ICMCS
2005
IEEE
15 years 3 months ago
2005
IEEE
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...