205 search results - page 12 / 41 » Clock gating architectures for FPGA power reduction |
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ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
ISPASS
2005
IEEE
15 years 5 months ago
2005
IEEE
We have previously presented Qsilver, a flexible simulation system for graphics architectures. In this paper we describe our extensions to this system, which we use— instrument...
FCCM
2008
IEEE
15 years 6 months ago
2008
IEEE
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
DAC
2005
ACM
2005
ACM
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
16 years 22 days ago
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
ISLPED
2003
ACM
15 years 5 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...