205 search results - page 15 / 41 » Clock gating architectures for FPGA power reduction |
88
Voted
TVLSI
2010
14 years 4 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important crite...
104
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FPL
2003
Springer
15 years 2 months ago
2003
Springer
Distributed Arithmetic techniques are widely used to implement Sum-of-Products computations such as calculations found in multimedia applications like FIR filtering and Discrete Co...
FPGA
1997
ACM
15 years 1 months ago
1997
ACM
ct High-capacity FPGAs pose device architects with a variety of problems. The most obvious of these problems is interconnect capacity. Others include interconnect performance, cloc...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...