205 search results - page 18 / 41 » Clock gating architectures for FPGA power reduction |
CORR
2010
Springer
14 years 9 months ago
2010
Springer
Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the soft...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register c...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
DAC
1995
ACM
15 years 1 months ago
1995
ACM
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...