205 search results - page 19 / 41 » Clock gating architectures for FPGA power reduction |
123
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FPGA
2003
ACM
15 years 5 months ago
2003
ACM
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
115
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VLSID
2003
IEEE
16 years 6 days ago
2003
IEEE
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...
102
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DAGSTUHL
2006
15 years 1 months ago
2006
Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the p...
VLSI
2007
Springer
15 years 6 months ago
2007
Springer
Abstract— In this paper, a low-power deblocking filter architecture for H.264/AVC is proposed. A hybrid filtering order has been adopted to boost the speed of the deblocking ...
103
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TVLSI
2008
14 years 11 months ago
2008
With the density of FPGAs steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpo...