205 search results - page 21 / 41 » Clock gating architectures for FPGA power reduction |
133
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ERSA
2009
14 years 9 months ago
2009
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
VLSID
2006
IEEE
16 years 6 days ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
115
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IPPS
2010
IEEE
14 years 9 months ago
2010
IEEE
Multi-pattern string matching remains a major performance bottleneck in network intrusion detection and anti-virus systems for high-speed deep packet inspection (DPI). Although Aho...
109
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DAC
2002
ACM
16 years 24 days ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
ISCAS
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract—This paper presents a method to investigate powerperformance tradeoffs in digital pipelined designs. The method is applied at the architectural level of the design. It w...