205 search results - page 22 / 41 » Clock gating architectures for FPGA power reduction |
DAC
2007
ACM
16 years 25 days ago
2007
ACM
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...
DATE
2004
IEEE
15 years 3 months ago
2004
IEEE
When an application or external environmental conditions cause a chip's cooling capacity to be exceeded, dynamic thermal management (DTM) dynamically reduces the power densit...
DAC
2007
ACM
16 years 25 days ago
2007
ACM
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep tran...
DSD
2008
IEEE
15 years 6 months ago
2008
IEEE
An architecture and VLSI implementation of a new block cipher called Curupira is presented in this paper. This cipher is suitable for wireless sensors and RFID applications. Our 0...
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DAC
2006
ACM
16 years 24 days ago
2006
ACM
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...